Motivation
The CMOSAIC project is a genuine opportunity to contribute to the realization of arguably the most complicated system that mankind has ever assembled: a 3D stack of computer chips with a functionality per unit volume that nearly parallels the functional density of a human brain. CMOSAIC's aggressive goal is to provide the necessarily 3D integrated cooling system that is the key to compressing almost 1012 nanometer sized functional units (1 Tera) into one cubic centimeter with a 10 to 100 fold higher connectivity than otherwise possible. Even the most advanced air-cooling methods are inadequate for high performance 3D-IC systems where the main challenge is to remove the heat produced by multiple stacked dies in a 1-3 cm3 volume, each layer dissipating 100-150 W/cm2. State-of-the-art single phase liquid and two- phase cooling systems, using specifically designed microchannel arrangements, and employing coolants ranging from liquid water and two-phase environmentally friendly refrigerants to novel engineered nano-fluids offer significant advantages in addressing heat removal challenges leading to practical 3D systems. CMOSAIC aims at developing the engineering science base that will enable a new state of the art in high density electronics cooling.
Figure 1: 3D-IC with through-silicon vias (TSVs) and inter-layer cooling channels that is enclosed in a sealed case
Specifically, this project brings together internationally recognized experts of leading Swiss universities and industry (EPFL, ETH Zurich and IBM Research Laboratory in Rüschlikon) to thoroughly investigate this interdisciplinary problem at different levels (architecture, microfabrication, liquid cooling, two-phase cooling, nano-fluids). These experts are joining forces to research the related physics and to develop the necessary thermal/electronic computational tools/methods. The project includes an intensive experimental program, consisting of challenging flow visualizations and heat transfer measurements in microchannel systems of hydraulic diameter often comparable to or smaller than that of a human hair, with complex fluids flowing through them. It also targets the development of novel theoretical models explaining the physics and new electronics packing models together with new micro- manufacturing processes. The verification of the proposed novel approaches coming out of this project will be conducted using several prototypes that will be built and tested. With respect to the Nano-Tera.CH proposal, this project addresses the vertical axis of micro/nanoelectronics, particularly the aspect of system integration. Specifically, the results of this project will be a significant step toward "achieving system complexities that are two-to- three orders of magnitude higher than today's state-of-the-art", by developing the fundamental understanding, methods and tools required for efficient and reliable design of true 3D integrated circuit systems.
There are four main challenges to the continued development of the computer industry with respect to Moore's law that will be resolved here are: power density, interconnect speed, interconnect density and integrated cooling. Electrical interconnect density and communication bandwidth between chips have become highly critical for processors as the number of transistors per layer and the number of layers in a 3D stack increase. There is thus a direct spatial competion among the heat dissipating components (processors, memory, interconnections, etc.) on each layer, the placement of the vias connecting the layers, and the placement of the microchannel cooling channels, whose optimal solution is thus a 3D mosaic. The solution promises to be not only cost effective but also Kyoto friendly.
The Laboratory of Thermodynamics in Emerging Technologies (LTNT) at ETH Zurich performs computational modeling of heat and mass-transfer in such microchannel networks. The investigation is conducted in close cooperation with IBM Zurich Research Laboratory which provides experimental data for the model development and validation.
Goals
1) Better understanding of conjugate heat transfer in micro pin array:
- CFD modeling of flow and temperature around representative set of individual pin elements (conjugate heat transfer problem)
- Study the inlet, outlet and wall effect on the heat transfer in micro pin array
- Build an averaged two-dimensional model of the conjugate heat transport in individual layer
- Optimization of heat transport in 3D stack via various arrangement of chips within the individual layers
Figure 2: Simulation of flow around a single pin
2) Modeling of power map optimized fluid network:
- Porous medium approximation of flow in the layer between two wafers
- Modeling of turbulent porous medium flow based on detailed simulations of turbulent flow around pillars. Non-equilibrium temperature models
- Modeling of anisotropic layer porosity as an option to direct the flow to hot spots
Figure 3: Uniform and non-uniform TSV distribution
