IBM unveils Power8 and OpenPower pincer attack on Intel’s x86 server monopoly

 

IBM has taken the wraps off the first servers that are powered by its monstrously powerful Power8 CPUs. With more than 4 billion transistors, packed into a stupidly large 650-square-millimeter die built on IBM’s new 22nm SOI process, the 12-core (96-thread) Power8 CPU is one of the largest and probably the most powerful CPU ever built. In a separate move, IBM is opening up the entire Power8 architecture and technical documentation through the OpenPower Foundation, allowing third parties to make Power-based chips (much like ARM’s licensing model), and to allow for the creation of specialized coprocessors (GPUs, FPGAs, etc.) that link directly into the CPU’s memory space using IBM’s new CAPI interface. You will not be surprised to hear that Nvidia, Samsung, and Google — three huge players among hundreds more who are beholden to Intel’s server monopoly — are core members of the OpenPower Foundation. The Power8 CPU and the OpenPower Foundation are the cornerstones of a very big, well-orchestrated plan to finally put an end to x86′s reign, and place a fairer, more powerful architecture at the head of the server table.

First, we should talk about the new Power8 chip. There are 12 CPU cores, each with 512KB of L2 SRAM and 8MB of L3 EDRAM, for a total of 6MB L2 and 96MB L3 cache respectively. There is then a further 230GB/sec of bandwidth to 1TB of DRAM. Whereas each Intel Xeon core is capable of two-way simultaneous threading, and Power7+ cores can do four threads, Power8 ups the ante to eight simlutaneous threads (SMT). As you’d expect, other parts of the chip have been similarly expanded to cater for the Power8′s massive parallelism: There are eight decoders (up from 6), six dispatches per clock cycle, a doubling of load units (4), the data cache can now process four 128-bit transactions per cycle, and the bus width between the L2 and data cache is now 512 bits. Take a look at the block diagram below and be awed by its massive parallelism and throughput.

IBM Power8 microarchitecture block diagram [Image credit: The Linley Group]

We expect the Power8 will eventually be capable of clock speeds around 4.5GHz, with a TDP in the region of 250 watts. At this speed, the Power8 CPU will be around 60% faster than the Power7+ in single-threaded applications, and more than two times faster in multithreaded tasks. In certain cases, IBM says the Power8 is capable of analyzing Big Data workloads between 50 and 1,000 times faster than comparable x86 systems (the same amount of RAM, the same number of cores).

Compared to its competitors (Power 7+, the Oracle Sparc T5, the Intel Xeon), the Power8 is anywhere between two and three times more processing power per socket. This is mostly due to the massive thread count (96 vs. 30 for the latest 15-core E7-8890 v2 Xeon), and utterly insane memory bandwidth (230GB/sec vs. 85GB/sec). In terms of performance per watt, though, the Xeon (~150W TDP) is probably just ahead of the Power8 — but in general, when you’re talking servers, power consumption generally plays second fiddle to performance density (how many gigaflops you can squeeze out of a single server).

IBM Power8 CPU die, labeled

Beyond raw SPECint and SPECfp performance, Power8 also introduces CAPI (Coherence Attach Processor Interface). CAPI is a direct link into the CPU, allowing peripherals and coprocessors to communicate directly with the CPU, bypassing (substantial) operating system and driver overheads. CAPI is similar to Intel’s QPI, but where QPI is closed and proprietary, IBM is opening up CAPI to third parties. IBM’s Power Systems CTO, Satya Sharma, told me in an interview that in the case of flash memory attached via CAPI the overhead is reduced by a factor of 20. More importantly, though, CAPI can be used to attach coprocessors — GPUs, FPGAs — directly to the Power8 CPU for some truly insane workload-specific performance boosts. It is due to these CAPI-attached coprocessors that a Power8 system can be 1,000 times faster than a comparable x86 system.

 

The OpenPower Foundation

While the Power8 chip is veritably beastly, it will take a lot more than a fancy piece of hardware to dislodge Intel x86 as the undisputed king of servers (Intel chips currently power somewhere in the region of 95% of all servers.) What IBM needs is a full top-to-bottom Power architecture stack, from first-party and third-party hardware, through to a broad, healthy ISV (independent software vendor) ecosystem. This is where the OpenPower Foundation comes in.

Basically, IBM is making the Power8 architecture and detailed technical documentation open to members of the Foundation. Currently, the foundation consists of Altera, Google, Nvidia, Micron, Samsung, Tyan, ZTE, and others. Each of these members will use the Power documentation in different ways. Altera is developing FPGAs that connect directly into the Power8 chip via CAPI, to provide stupendous speed-ups for specific tasks. Tyan, with help from Google, will create third-party motherboards that are compatible with the Power8 chip, with the goal of producing cheap, Power8-based machines for internet-scale server farms. Nvidia, like Altera, will develop a Tesla-like GPU coprocessor that connects directly to the CPU via CAPI. Suzhou will license the Power architecture to make its own Power8-compatible chips for China’s domestic server market.

Taking down Intel

IBM’s giant Power8 chip, being held in a normal-sized hand.

The hope is that, by cultivating a broad hardware and software ecosystem, Power will be able to challenge Intel in the server space. IBM wants to be the ARM of servers, basically: In much the same way that ARM’s open architecture and licensing model allowed it to squash Intel in the mobile and embedded spaces, IBM wants to do the same thing in servers.

Usually I would say that it’s a fool’s errand to challenge Intel, but if anyone can do it, it’s IBM. There is a lot of antipathy towards Intel and the strategies it has used to dismantle everyone and everything that has threatened to disrupt its dominion over the computing industry. Server vendors (IBM, HP, Dell) and internet-scale service providers (Google, Facebook) use x86 chips, but only because Intel has ensured that there’s no other viable option. I don’t think there’s a single company that doesn’t want to get out from underneath the choking heft of Intel x86 — and now, at long last, IBM might be offering a way out. If the surge in mobile computing has taught us anything it’s that Intel isn’t unbeatable — that there’s a chink in its armor that IBM and the rest of the OpenPower Foundation think it can exploit. “We are entering some new spaces,” Sharma told me. “It’s a transformational event for Power. It’s going to take Power to new spaces we haven’t gone before.”

New Power8 servers, being tended to by a couple of IBMers

IBM also announced today that Canonical’s Ubuntu Server will be available for all Power8-based systems, and that it will continue to invest in Linux (IBM/Power is historically Unix-focused, not Linux). “Now is the time to expand into the Linux space,” Sharma said as our interview was wrapping up. “Ubuntu is now one of the primary targets for Power.”

The first Power8 servers will be available from June 10, with a range of 1- and 2-socket 2U and 4U models. The Power S812L and Power S822L (both 2U) will exclusively run Linux. The flagship of the Power8 line is the Power S824, a 4U design with two CPU sockets, maxing out at 24 cores (192 threads) and 1TB of RAM. The low-end Linux-powered S812L server starts at $8000. (IBM wouldn’t tell us the exact pricing of a standalone Power8 CPU, but it’s probably in the region of $5,000.)

Computers that will see, hear, smell: Next, world domination?

 

By Deborah Netburn

December 17, 2012, 3:15 p.m.

IBM's 5 in 5 -- a list of five innovations that could change the world in five years -- focuses on how computers are developing the ability to taste, touch, hear, see and listen just like humans do, except way better.

It is kind of exciting and kind of terrifying, but mostly just really cool.

For example, Hendrik Hamann, a research manager of physical systems for IBM, describes a smartphone that could use a computerized nose to "smell" if we are sick. Forget the thermometer and the doctor's visit -- we will simply breathe into our cellphones to find out if we have the flu.

Robyn Schwartz describes how smartphones of the future might use vibrations to allow us to virtually "touch" a piece of material and feel its texture. This technology is already available for some video games, but she imagines a world in which online shoppers don't just see and read about an item of clothing, they can stroke it as well.

Dimitri Kanevsky, a research scientists at IBM, explains that sound sensors may be able to "hear" an earthquake coming, long before a human would sense it. And John Smith explains that a computer that knows how to make sense of what it can "see" would be able to diagnose a cancerous growth on your skin. 

Finally, Lav Varshney describes a computer program that can learn what pleases your taste buds on a molecular level, and can then design healthy recipes that taste delicious to you, based on that information. 

So far, so cool, right? But what made me feel a little scared was this paragraph in an essay by IBM's chief innovation officer, Bernard Meyerson, about this year's 5 in 5.

He writes:

"In the coming years, computers will become even more adept at dealing with complexity. Rather than depending on humans to write software programs that tell them what to do, they will program themselves so they can adapt to changing realities and expectations. They’ll learn by interacting with data in all of its forms -- numbers, text, video, etc. And, increasingly, they’ll be designed so they think more like the humans."

Later in the essay he explains that IBM is not interested in replacing human thinking with machine thinking. He actually says it twice. Instead he imagines a future where humans and machines work together to make the world a better place. 

I hope that prediction, at least, is correct.

HP unveils PowerCARD payment management software

06 November 2012  |   Source: HP

       

HP today announced that banks, retailers and telecom operators can now boost the cost-effectiveness of their card operations with PowerCARD payment management software.

With this agreement, HP now offers customers a card payment solution across Europe, Middle East and Africa. This solution complements HP's existing card services utilities which are already available to clients in the Americas and in the Asia-Pacific regions.

HPS, an HP AllianceONE partner, is a leading payment software company who currently provides state-of-the-art card, ATM and POS management systems for over 320 financial institutions in 70 countries. As part of the HP AllianceONE program, HP and HPS will jointly offer outsourced payments solutions based on PowerCARD software in the Europe, Middle East and African (EMEA) region. HP offers a broad solution set for both in-house processing and outsourced services and works with clients globally to define the appropriate strategic fit for their cards and payments business.

"Organisations now have the opportunity to improve their card solutions by replacing legacy hardware and software with something much more flexible and cost-effective," says Ed Adshead-Grant, EMEA card and payments practice head, HP. "HP is viewed by many as the OEM of the payment industry, and our tests confirm PowerCARD as a robust, scalable complement to HP's own Payments Solutions for the EMEA region. Organisations of all sizes can now boost the cost-effectiveness and competitive positioning of their card issuing, switching and acquiring solutions."

In a series of rigorous tests conducted over five weeks on the latest HP Superdome2 servers, the HP European Performance Centre scaled PowerCARD payment software up to 100 million accounts with processing cycles of 3,000 transactions per second for up to 5,000 concurrent users. Performing online data and batch processing with economical HP-UX server infrastructures ensures that resource is readily available, and enables changes to products and services to be delivered in a fraction of the time taken by a mainframe solution.

"The HP tests clearly demonstrate that the reliability, availability and scalability required for 24x7 card processing services can be achieved by running PowerCARD software on HP-UX servers," says Abdeslam Alaoui, Managing Director, HPS. "The collaboration between HPS and HP in this project has been excellent. As an AllianceOne Partner, HPS will continue working with HP to deliver modernisation programs in electronic payment for any financial institution that is looking to win market share or escape the technology legacy trap."

HP AllianceONE is a comprehensive partner program for technology companies focused on HP's Converged Infrastructure strategy of providing a shared services model to deliver secure, best-in-class applications. 

Home How To How to delete yourself from the Internet

 

You may not feel like the flotsam and jetsam that make up the facts of your life are important, but increasingly companies are using that dry data to make your every online step as indelible as if written in blood. Here's how to take back your digital dignity.

by Seth Rosenblatt   April 19, 2012 6:19 PM PDT

The Internet companies that power your online life know that data equals money, and they're becoming bolder about using that data to track you. If they get their way, your every online step would be not only irrevocable, but traceable back to you. Fortunately, there are some positive steps you can take to reclaim your online history for yourself.

The online privacy software company Abine, which makes Do Not Track Plus, also offers a service called DeleteMe, which removes your data from numerous tracking sites and keeps it from coming back. In an unusual gesture, though, they've made public how to do for yourself everything that DeleteMe does. Here's my take on their advice.

Be warned, though. The following are not easy instructions, and it's not because they're technically complex. They require a tenacity and wherewithal that is likely to either exhaust you, drive you borderline bonkers, or both. (And no, I haven't followed the instructions to remove myself because it's essential to my job that I can be found by strangers.)

Step 1: Prepare yourself: You're going to have to be polite.
These instructions require patience for the antics of others and determination to get the job done. It's not a bad idea to get something inanimate to take your frustrations out on, because often getting your data successfully removed or changed will require the good faith of the person you're dealing with. Things are not likely to go your way the first time around.

Step 2: Aggressively track sites that aggressively track you.
This is where the DeleteMe service comes in. They currently charge you $99 to un-track you from the tracking data clearinghouses, which in turn sell your data to others entities. You can follow Abine's list of services and do the deed yourself, and that means writing many e-mails, sending numerous faxes, and placing enough phone calls to make you wish for a time machine so you can go back to the 19th century to do violence unto Alexander Graham Bell.

One thing that isn't clear from Abine's list is that most of these data aggregators will re-add you within a few months, so I recommend at least bi-annual checks to see if they've sucked up your data again. Be tenacious, be polite, and if this is important to you, stick with it until you get what you want.

If you're concerned about privacy and people making connections between your birthday, your address, and your Social Security number, you owe it to yourself to perform at least one Web search for your name and see what comes up. You might be unpleasantly surprised.

Step 3: To protect your reputation, removal must be done from the source.
To get Google, Bing, and other search engines to notice a change in information as it is presented on the Web, the original site hosting that information must change. It doesn't matter which site is the source. It could be Facebook, or a local blog, or a gaming forum. If it's showing up in search results, it has little to do with the search engine and everything to do with the site of origin. Once that site has changed, then you'll see a change in the search results.

Getting something removed from a site is not a scientific process, even though you must be methodical about it. Ask politely, and as I noted above, you're likely to have to ask more than once and using more than one way to communicate. You likely will have to be a rake at the gates of Hell, but one that uses words like "please" and "thank you".

Look for the name of a writer, or Web site manager, and if no contact information is listed, do a WhoIs search by typing "whois www.site-name.com". Be sure to include the quotes. That will tell you who registered the site, which is a good place to start on smaller Web sites. Look for phone numbers, e-mail, and fax numbers, and follow up your initial communication.

Once you have a name, even if you can't find a phone number or e-mail, you can probably take an educated stab at one. Use a site like E-mail Format to help you out. And in your e-mail, be sure to explain clearly, concisely, and logically why your request ought to be honored.

A willingness to compromise can get you better results, too. If, for example, your initial request to fully remove your name gets refused, see if asking to have your identity anonymized will work. And if one person at the site you've contacted keeps stalling you, see if there's another you can contact instead.

Step 4: Get Google to hustle on search engine changes.
If you've been successful in changing a site, but Google is still showing the older version, you can use Google's URL Removal Tool to accelerate the process. Note that this will require a Google account, and that if you get Google to change, you're going to have to submit requests to other major search engines like Bing separately.

Step 5: Paint over the bad with good.
In cases where you can't get the site to remove the content that's negatively affecting your reputation, you can create new, fresh, positive content to counteract it. The idea is that the Positive You will bury the Negative You. Rick Santorum is a great example of how this can work in reverse, and no, I'm not going to link to it for you.

You can also use social-networking sites to bury bad news. From About.Me to Flickr to Twitter, social networks tend to rank highly in search results. By creating and maintaining accounts that use your real name, you can elevate the social networking results for your name and, ideally, drop the results you want to bury onto the second page of results. Since studies show that second-page results are viewed significantly less often than first-page, this could be a successful burying strategy.

However, a key component of this is linking the networks, so be prepared to do far more social networking than you had been.

Step 6: Go (politely) nuclear. Get a lawyer.
If you suspect something is actually defamatory, seek out legal advice. Gather your evidence, be polite and firm, and seek out someone who can guide you through the thorny legal thicket. This will also depend on your country -- England has much broader defamation and libel laws than the United States does -- and your budget.

There is no foolproof method for changing how you're presented on the Internet, whether looking at purely personally-identifiable data or the much more subjective presentation of your personal reputation. However, if these are concerns of yours, you're not alone out there, and these six steps will give you concrete actions you can take to reclaim your identity and repair how others see you.

SKYNET : SyNAPSE, IBM envisage le cerveau gravé sur du Silicium

 

IBM a conçu deux CPU qui sont structurés comme un cerveau humain même s’ils sont encore loin d’en avoir les capacités (pour le moment). Ces deux puces s’inscrivent dans cadre du projet SyNAPSE ( Systems of Neuromorphic Adaptive Plastic Scalable Electronics). Celui-ci pourrait bien être à l’origine d’une nouvelle ère dans l’informatique. Non, il ne s’agit pas de science-fiction.
Il s’agit de deux puces expérimentales. Une architecture imitant celle du cerveau permettrait de développer l’informatique cognitive. La machine qui embarquera un tel CPU pourrait traiter l’information à la manière d’un cerveau humain, ce qui lui permettrait d’apprendre et de conclure. Elle serait aussi plus efficace que les actuels ordinateurs : consommation plus faible et encombrement réduit.
On pense bien entendu à HAL dans 2001, l’odyssée de l’espace.
Chacune des deux puces expérimentales est gravée en 45nm et dispose de 256 neurones. L’une dispose de 262,144 synapses qui sont programmables. La deuxième puce possède 65,536 synapses ayant la capacité d’apprendre. Dans un ordinateur, les interconnexions sont fixes ; le CPU est tel qu’il a été gravé alors qu’avec ce nouveau type de CPU, les connexions peuvent évoluer soit par apprentissage, soit par programmation (on a les deux cas ici avec ces deux puces expérimentales).
A l’avenir, IBM envisage de créer des CPU avec des dizaines de millions de neurones et des trillions (un trillion est un milliard de milliards) de synapses. L’ensemble consommerait un kilowatt et occuperait un volume de deux litres. Un cerveau possède toutefois 10^11 (100 milliards) de neurones et 1000 synapses par neurone.
De tels ordinateurs seraient capable de résoudre des opérations sur lesquelles les ordinateurs actuels bloquent. La puissance de calcul phénoménale qu’ils développeraient leur permettraient de traiter des millions d’informations et de prédire très précisément la météo et des catastrophes naturelles par exemple.
Mais le plus incroyable, c’est peut-être la capacité qu’auraient ces ordinateurs à ne plus être dépendants d’un informaticien puisqu’ils auraient la faculté d’apprendre par eux-mêmes et de tirer des conclusions.
Le Super-ordinateur Watson de Big Blue, s’il n’embarque pas ce type de CPU, avait déjà laissé entrevoir un tel comportement cognitif.

The curious incident of Oracle and HP-UX on Itanium

 

The curious incident of Oracle and HP-UX on Itanium

Comment When I saw the news on Wednesday morning, I thought I had picked the wrong week to give up sniffing glue. Or maybe Oracle did. Either way, Oracle’s announcement that it is halting development on HP-UX/Itanium versions of its products touched off a firestorm of phone calls, emails and tweets that just won’t let up.

TPM covered the basics in his excellent story here. Snarky ‘Itanic’ jibes in the headlines aside, HP-UX based Unix systems are in use in a large number of customer data centers, as are IBM Power Unix systems and Oracle SPARC boxes.

These big iron boxes have moved from being the hot new thing a decade ago into more of a mission-critical, mainframe-esque role in mid-sized and large data centers.   What first struck me about the Oracle press release is the claim that “Intel management made it clear that their strategic focus is on their x86 microprocessor and that Itanium was nearing end of life”.

Funny, that directly contradicts what I’ve heard for years directly from Intel and HP. Intel has been more forthcoming about Itanium roadmaps, dates and specifications than at any time in recent memory. Oracle, by contrast, has reinforced its reputation as the North Korea of the server business … only without the charisma and cool Texaco flag.

Why would Intel publicly discuss Itanium roadmaps if it was near end-of-life? Why would it tell Oracle one thing about its plans and HP, industry analysts and the press another? Why would Intel do something that would make them look either deceptive or stupid? Answer: it wouldn’t. Intel doesn’t make those kinds of mistakes.

Gold in them thar processors

Intel is making good money on Itanium processors – more than enough to justify future development. HP is making good money on Integrity (HP-UX + Itanium) systems. Hell, even Oracle is making money on software installed on HP-UX systems. In fact, it is making even more since it tweaked licensing terms to jack up database pricing on HP Unix systems. So if everyone is making bank (including Oracle), why disrupt things now?

This is what Ellison meant when he said that Oracle wants to be the IBM of the 1960s

I think that Oracle simply wants to cut a competitor out of the Unix running and make a play for their installed base. I’ve been in the enterprise server business for more than 15 years now (God, I’m old). For the last five years, I’ve run comprehensive Unix vendor surveys among data center respondents.

They compare the major Unix vendors (HP, IBM and Sun/Oracle) on a wide variety of technical and customer support criteria. In general, IBM and HP tend to beat Sun/Oracle on the majority of questions, which include OS qualities, RAS, performance, and vendor support. (We’ll publish the results from our most recent survey in coming weeks.)

Our survey respondents also indicate that Oracle’s installed base isn’t very comfortable with Oracle’s plans, the way the company communicates those plans, or the support they receive This is quite a change from the Sun days, when most respondents may not have been all that wild about the systems, but they seemed to always like the company and the support it provided.

Let’s say I’m right, and Oracle is playing every card they can to build up its hardware business and drive customers away from HP. Why stop there? How long until it announces it is halting development on IBM AIX versions of its software? Or change the licensing terms to make it even more expensive to deploy on Power vs. any Oracle alternative? Taking it a bit further, is there an Oracle plan to find a way to charge customers a bit more if they run Oracle software on Dell, HP, or IBM x86 hardware? Maybe crank up the support costs a bit higher?

Lock-in

To me, this is the reality of what Ellison meant when he said that Oracle wants to be the IBM of the 1960s. Oracle wants to have the incredible margins that IBM enjoyed back then. It wants to have that lock-in that IBM had in the days when there were few alternatives and even fewer standards that would allow customers to easily move from vendor to vendor.

But we don’t live in the 1960s, or even in the 1990s. Back in the 90s and early 00s, Oracle had the power to push server vendors out of the business simply by announcing that it was moving its DB port to a vendor’s OS to second-tier status. If Oracle dropped support of an OS entirely, it was the kiss of death – something that was widely speculated about in vendor and customer communities.

But it’s a different world today. There are a lot of alternatives for HP-UX customers to consider. The current version of IBM’s DB2 database, for example, is fully supported on HP-UX.   There is also a difference in vendor scale today. It used to be easy for Oracle to bully small vendors like Sequent, Pyramid, Data General, NCR and even DEC. They could even intimidate the Unix brands of larger companies such as HP and IBM.

But  today’s systems vendors are larger, more diversified and have more options. Customers today are different too, more sophisticated and not as frightened when it comes to changing systems, databases, or applications. Perhaps most importantly, customers have greater control than ever over their IT choices.

Will Oracle’s gambit work? Will it result in greater system sales? Higher database sales on their own iron? Or will there be a backlash from customers who now see the Ghost of Christmas Future – Oracle tightening the screws and reducing their options until they buckle under and start buying Oracle iron to run Oracle software?

It’s too early to tell. But based on what I’m hearing from clients and what I’ve seen in my own research, I’m betting on backlash. ®

The curious incident of Oracle and HP-UX on Itanium

Two billion-transistor beasts: POWER7 and Niagara 3

     By Jon Stokes |

A 300mm Power 7 processor wafer

In years past, an ISSCC presentation on a new processor would consist of detailed discussion of the chip's microarchitecture (pipeline, instruction fetch and decode, execution units, etc.), along with at least one shot of a floorplan that marked out the location of major functional blocks (the decoder, the floating-point unit, the load-store unit, etc.). This year's ISSCC is well into the many-core era, though, and with single-chip core counts ranging from six to 16, the only elements you're likely to see in a floorplan like the two below are cores, interfaces, and switches. Most of the discussion focuses on power-related arcana, but most folks are interested in the chips themselves.

In this short article, I'll walk you through the floorplan of two chips with similar transistor counts—the Sun's Niagara 3 and IBM's POWER7. Most CPU geeks will already know a lot of the information I'll give below, but many readers will appreciate having it all together in one place.

Niagara 3: threads and I/O

Sun's Niagara 3

Sun's 1 billion-transistor, 16-core Niagara 3 processor is a great example of modern multiprocessor-turned-SoC (system on a chip). Everything about this design is focused on pushing large numbers of parallel instruction streams and data streams through the processor socket at once. The shared cache is small, the shared pipes are wide, and the end result is a chip that's all about maintaining a high rate of flow, and not one that's aimed at collecting a large pile of data and chipping away at it with heavy equipment.

Each of the 16 individual SPARC cores that make up Niagara 3 support up to eight simultaneous threads of execution, for a total of 128 threads per chip. Logically, the chip is laid out so that all of the cores communicate with a unified 6MB L2 cache via a crossbar switch that's placed in the middle of the chip. This combination of cores and L2 connected via a switch forms the basic compute architecture of the SoC.

So that the chip can talk to the outside world, the L2 caches are connected to a variety of I/O interfaces: memory, PCIe, 1G/10G Ethernet, and coherency links. All told, those links can push a total of 2.4Tb/s worth of data through a single Niagara 3 socket—that's a lot of bandwidth, but you need it to feed that many threads. Let's take a quick look at each of these I/O links in turn.

Coherence: Niagra 3's coherence links are the equivalent of the QuickPath Interconnect (QPI) on Intel's Nehalem parts, or of HyperTransport for AMD. These links can be used to connect up to four of the chips together without any additional routing chips (this is what's meant by saying Niagara 3 can be used in a four-socket glueless configuration). Each Niagara 3 chip has two 1.6GHz coherence controllers, which are connected to six coherence links. Each individual link consists of 14 unidirectional lanes that give the link a total bandwidth of 9.6Gb/s.

Memory: Also attached to the L2 is are two DDR3 memory controllers, each of which hosts two memory channels, for a total of four channels of DDR3.

PCIe and Ethernet: A PCIe controller supports two 5Gb/s PCIe ports, and an Ethernet controller supports two 1G/10G Ethernet ports.

IBM's POWER7

IBM's POWER7

At 1.2 billion transistors, IBM's new 45nm POWER7 processor is only a little bigger than Niagara 3, but it couldn't be more different. If Niagara 3 is an army of guys with shovels, POWER7 is a giant bulldozer.

POWER7 has only half the cores (eight) and one quarter of the threads (32) of Sun's chip, but that doesn't mean it falls short in the horsepower department. Each POWER7 core has a ton of very fast execution hardware, and the overall layout of the machine's very wide execution core is a straightforward evolution of the design that I first described in a series of articles on the PowerPC 970. (I talked more about POWER7's execution core in an earlier article comparing it to Intel's Tukwila Itanium.)

Where Niagra 3 keeps a large number of relatively weak cores busy by moving data onto and off of the chip using ample I/O resources, POWER7's approach to feeding a smaller number of much more robust cores is to cache large amounts of data on-chip so that the cores can grind through it in batches. This being the case, POWER7 has the most remarkable on-chip cache hardware of any processor on the market.

First in the chain is the 32KB L1 data cache, which has seen its latency cut in half, from four cycles in the POWER6 to two cycles in POWER7. Then there's the 256KB L2, the latency of which has dropped from 26 cycles in POWER6 to eight cycles in POWER7—that's quite a reduction, and will help greatly to mitigate the impact of the shared L3's increased latency.

The POWER7's L3 is its most unique feature, and, at 32MB, it's positively gigantic. IBM was able to cram such a large L3 onto the chip by making it out of embedded DRAM (eDRAM) instead of the usual SRAM. This decision cost the cache a few cycles of latency, but in exchange IBM got a 3.5x improvement in power efficiency and a 3x improvement in cache density. IBM has actually been talking up the use of eDRAM for on-chip cache since at least 2002, so in this regard POWER7 represents the fruition of years of work on this approach.

On the I/O side, POWER7 features two DDR3 memory controllers that can do up to 100GB/s total. The chip's SMP links (the same as Niagara's coherence links) can do 360GB/s (or almost 2.9Tb/s) of bandwidth, but this amount appears to be divided between internal and external SMP links. The chip doesn't contain the other I/O options—PCIe or Ethernet—that Niagara has.

Ultimately, these two server-class processors show that there are two very different ways to spend a billion transistors, and each design will be good for different applications. Sun's Niagara is aimed at networked server operations where lots of simultaneous, lightweight requests have to be serviced—databases, Web servers, and the like. In contrast, POWER7 has the horsepower to grind through a smaller number of more compute-intensive tasks at a high rate of speed. Both parts have their place in the server ecosystem of 2010.

 

 

3D Integrated Water Cooling of a Composite Multilayer Stack of Chips

 

Motivation

The CMOSAIC project is a genuine opportunity to contribute to the realization of arguably the most complicated system that mankind has ever assembled: a 3D stack of computer chips with a functionality per unit volume that nearly parallels the functional density of a human brain. CMOSAIC's aggressive goal is to provide the necessarily 3D integrated cooling system that is the key to compressing almost 1012 nanometer sized functional units (1 Tera) into one cubic centimeter with a 10 to 100 fold higher connectivity than otherwise possible. Even the most advanced air-cooling methods are inadequate for high performance 3D-IC systems where the main challenge is to remove the heat produced by multiple stacked dies in a 1-3 cm³ volume, each layer dissipating 100-150 W/cm². State-of-the-art single phase liquid and two- phase cooling systems, using specifically designed microchannel arrangements, and employing coolants ranging from liquid water and two-phase environmentally friendly refrigerants to novel engineered nano-fluids offer significant advantages in addressing heat removal challenges leading to practical 3D systems. CMOSAIC aims at developing the engineering science base that will enable a new state of the art in high density electronics cooling.

Figure 1: 3D-IC with through-silicon vias (TSVs) and inter-layer cooling channels that is enclosed in a sealed case

Specifically, this project brings together internationally recognized experts of leading Swiss universities and industry (EPFL, ETH Zurich and IBM Research Laboratory in Rüschlikon) to thoroughly investigate this interdisciplinary problem at different levels (architecture, microfabrication, liquid cooling, two-phase cooling, nano-fluids). These experts are joining forces to research the related physics and to develop the necessary thermal/electronic computational tools/methods. The project includes an intensive experimental program, consisting of challenging flow visualizations and heat transfer measurements in microchannel systems of hydraulic diameter often comparable to or smaller than that of a human hair, with complex fluids flowing through them. It also targets the development of novel theoretical models explaining the physics and new electronics packing models together with new micro- manufacturing processes. The verification of the proposed novel approaches coming out of this project will be conducted using several prototypes that will be built and tested. With respect to the Nano-Tera.CH proposal, this project addresses the vertical axis of micro/nanoelectronics, particularly the aspect of system integration. Specifically, the results of this project will be a significant step toward "achieving system complexities that are two-to- three orders of magnitude higher than today's state-of-the-art", by developing the fundamental understanding, methods and tools required for efficient and reliable design of true 3D integrated circuit systems.

There are four main challenges to the continued development of the computer industry with respect to Moore's law that will be resolved here are: power density, interconnect speed, interconnect density and integrated cooling. Electrical interconnect density and communication bandwidth between chips have become highly critical for processors as the number of transistors per layer and the number of layers in a 3D stack increase. There is thus a direct spatial competion among the heat dissipating components (processors, memory, interconnections, etc.) on each layer, the placement of the vias connecting the layers, and the placement of the microchannel cooling channels, whose optimal solution is thus a 3D mosaic. The solution promises to be not only cost effective but also Kyoto friendly.

The Laboratory of Thermodynamics in Emerging Technologies (LTNT) at ETH Zurich performs computational modeling of heat and mass-transfer in such microchannel networks. The investigation is conducted in close cooperation with IBM Zurich Research Laboratory which provides experimental data for the model development and validation.

Goals

1) Better understanding of conjugate heat transfer in micro pin array:

• CFD modeling of flow and temperature around representative set of individual pin elements (conjugate heat transfer problem)
• Study the inlet, outlet and wall effect on the heat transfer in micro pin array
• Build an averaged two-dimensional model of the conjugate heat transport in individual layer
• Optimization of heat transport in 3D stack via various arrangement of chips within the individual layers

Figure 2: Simulation of flow around a single pin

2) Modeling of power map optimized fluid network:

• Porous medium approximation of flow in the layer between two wafers
• Modeling of turbulent porous medium flow based on detailed simulations of turbulent flow around pillars. Non-equilibrium temperature models
• Modeling of anisotropic layer porosity as an option to direct the flow to hot spots

Figure 3: Uniform and non-uniform TSV distribution